SM320VC5510A-HiRel Overview
Key Features
- 5-ns Instruction Cycle Time
- 200-MHz Clock Rate
- One/Two Instructions Executed per Cycle
- Dual Multipliers [Up to 400 Million Multiply-Accumulates Per Second (MMACS)]
- Two Arithmetic/Logic Units
- One Internal Program Bus
- Three Internal Data/Operand Read Buses
- Two Internal Data/Operand Write Buses D Instruction Cache (24K Bytes) D 160K x 16-Bit On-Chip RAM Composed of
- Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
- Asynchronous Static RAM (SRAM)
