SM34020APCM40 Datasheet PDF

Texas Instruments SM34020APCM40

the SM34020APCM40 Address Space − Implicit Addressing − Prefetch for Enhanced Read Access SGLS361 − JULY 2006 D Programmable CRT Control − Composite Synchronization Mode − Separate Synchronization Mode − Synchronization to External Synchronization D Direct Support for Special Features of 1M VRAMs − Load Write Mask − Load Color Mask − Block Write − Write Using the Write Mask D Flexible Multiprocessor Interface D 144-Pin PCM Quad Flat Package (QFP) 108 109 PCM PACKAGE ( TOP VIEW ) 73 72 144 1 37 36 description The SM34020APCM40 graphics system processor (GSP) is the second generation of an... With a built-in instruction cache (I-cache), the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the SM34020APCM40 provides user-programmable control of the CRT interface, as well as the memory interface [both standard DRAM and multiport video RAM (VRAM)]. The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable width data fields (1 to 32 bits).