SMOMAPL138B-HIREL Description
SLVSAQ9B JANUARY 2011 REVISED JULY 2013 SMOMAPL138B Low-Power Applications Processor Check for Samples: SMOMAPL138B-HiRel 1 SMOMAPL138B Low-Power Applications Processor 1.1.
SMOMAPL138B-HIREL Key Features
- Highlights
- pact 16-Bit Instructions
- Dual Core SoC
- C674x Two Level Cache Memory Architecture
- 375-MHz ARM926EJ-S™ RISC MPU
- 32K-Byte L1P Program RAM/Cache
- 375-MHz C674x Fixed/Floating-Point VLIW
- 32K-Byte L1D Data RAM/Cache
- 256K-Byte L2 Unified Mapped RAM/Cache
- Enhanced Direct-Memory-Access Controller