SMV512K32-SP Description
The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: The master device selection provides user defined autonomous EDAC scrubbing options.
SMV512K32-SP Key Features
- 20-ns Read, 13.8-ns Write Through Maximum Access Time
- Functionally patible With mercial 512K x 32 SRAM Devices
- Built-In EDAC (Error Detection and Correction) to Mitigate Soft Errors
- Built-In Scrub Engine for Autonomous Correction
- CMOS patible Input and Output Level, Three State Bidirectional Data Bus
- 3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE
- Radiation Performance (1)
- Uses Both Substrate Engineering and Radiation Hardened by Design (HBD) (2)
- TID Immunity > 3e5 rad (Si)
- SER < 5e-17 Upsets/Bit-Day (Core Using EDAC and Scrub) (3)