Texas Instruments SN10KHT5539
The SN10KHT5539 is characterized for operation from 0°C to 75°C.| Part No. | SN10KHT5539 |
|---|---|
| Datasheet | SN10KHT5539 Download |
| Manufacturer |  Texas Instruments |
| Description | Octal ECL-to-TTL Translator |
| Buy | Stock & Price |
● 10KH Compatible
● Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers
● ECL and TTL Output-Enable Inputs
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise
● Package Options Include “Small Outline” Packages and Standard Plastic 300-mil DIPs SN10KHT5539 OCTAL ECLĆTOĆTTL TRANSLATOR WITH OPENĆCOLLECTOR OUTPUTS SDZS007 − JANUARY 1990 − REVISED OCTOBER 1990 DW OR NT PACKAGE (T0P VIEW) Y1 Y2 Y3 Y4 VCC GND GND GND Y5 Y6 Y7 Y8 1 2 3 4 5 6 7 8 9 10 11 12 24 A1 23 A2 22 A3 21 A4 20 OE2 (TTL) 19 VEE 18 GND 17 OE1 (ECL) 16 A5 15 A6 14 A7 13 A8 description This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters while eliminating the need for 3-state overlap protection.
● Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers
● ECL and TTL Output-Enable Inputs
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise
● Package Options Include “Small Outline” Packages and Standard Plastic 300-mil DIPs SN10KHT5539 OCTAL ECLĆTOĆTTL TRANSLATOR WITH OPENĆCOLLECTOR OUTPUTS SDZS007 − JANUARY 1990 − REVISED OCTOBER 1990 DW OR NT PACKAGE (T0P VIEW) Y1 Y2 Y3 Y4 VCC GND GND GND Y5 Y6 Y7 Y8 1 2 3 4 5 6 7 8 9 10 11 12 24 A1 23 A2 22 A3 21 A4 20 OE2 (TTL) 19 VEE 18 GND 17 OE1 (ECL) 16 A5 15 A6 14 A7 13 A8 description This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters while eliminating the need for 3-state overlap protection.
