Datasheet4U Logo Datasheet4U.com

SN54ABT16833 - DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

Description

The ’ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses.

For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY).

📥 Download Datasheet

Datasheet preview – SN54ABT16833

Datasheet Details

Part number SN54ABT16833
Manufacturer Texas Instruments
File Size 833.78 KB
Description DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Datasheet download datasheet SN54ABT16833 Datasheet
Additional preview pages of the SN54ABT16833 datasheet.

📁 Similar Datasheet

  • SN54HC595J - 16-bit bus transceiver and transparant D-type latch (nexperia)
  • SN54LS00 - QUAD 2-INPUT NAND GATE (Motorola Inc)
  • SN54LS01 - QUAD 2-INPUT NAND GATE (Motorola Inc)
  • SN54LS02 - QUAD 2-INPUT NOR GATE (Motorola Inc)
  • SN54LS03 - QUAD 2-INPUT NAND GATE (Motorola Inc)
  • SN54LS04 - HEX INVERTER (Motorola Inc)
  • SN54LS05 - HEX INVERTER (Motorola Inc)
  • SN54LS08 - QUAD 2-INPUT AND GATE (Motorola Inc)
  • SN54LS09 - QUAD 2-INPUT AND GATE (Motorola Inc)
  • SN54LS10 - TRIPLE 3-INPUT NAND GATE (Motorola Inc)
Other Datasheets by Texas Instruments

Full PDF Text Transcription

Click to expand full text
SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D Flow-Through Architecture Optimizes PCB Layout D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Parity-Error Flag With Parity Generator/Checker D Register for Storage of Parity-Error Flag D Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center
Published: |