SN54ABT646 Datasheet | Texas Instruments

description SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E - JULY 1991 - REVISED JULY 1994 SN54ABT646 . . . JT PACKAGE SN74ABT646 . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) CLKAB 1 SAB 2 DIR 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 A8 11 GND 12 24 VCC 23 CLKBA 22 SBA 21 OE 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 B8 SN54ABT646 . . . FK PACKAGE (TOP VIEW) DIR SAB CLKAB NC VCC CLKBA SBA These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′ABT646. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. 4 3 2 1 28 27 26 A1 5 25 OE A2 6 24 B1 A3 7 23 B2 NC 8 22 NC A4 9 21 B3 A5 10 20 B4 A6 1112 13 14 15 16 17 1819 B5 A7 A8 GND NC B8 B7 B6 - No internal connection The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT646 is available...