Datasheet Summary
D Members of the Texas Instruments
Widebus+™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up and Power Down
D Released as DSCC SMD 5962-9557801NXD
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F
- JUNE 1992
- REVISED MAY 1997
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D High-Drive Outputs (- 32-mA IOH, 64-mA IOL) D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors...