SN54AHC273 Overview
Key Specifications
Output Type (varies by manufacturer): CMOS
Description
These devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse.
Key Features
- 1 Operating Range 2-V to 5.5-V VCC
- Contain Eight Flip-Flops With Single-Rail Outputs
- Direct Clear Input
- Individual Data Input to Each Flip-Flop
- Latch-Up Performance Exceeds 250 mA Per JESD 17
