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SN54AHCT16374, SN74AHCT16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCLS337I – MARCH 1996 – REVISED FEBRUARY 2000
D Members of the Texas Instruments
Widebus ™ Family
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Process
D Inputs Are TTL-Voltage Compatible D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
description
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SN54AHCT16374 Datasheet
