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SN54ALS137A, SN74ALS137A, SN74AS137 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
SDAS203C − APRIL 1982 − REVISED JANUARY 1995
• Combines Decoder and 3-Bit Address
Latch
• Incorporates Two Output Enables to
Simplify Cascading
• Package Options Include Plastic Small-
Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
description
The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/ demultiplexers with latches on the three address inputs. When the latch-enable (LE) input is low, the devices act as decoders/demultiplexers. When LE goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as LE remains high.