Datasheet Details
| Part number | SN54AS74A |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 1.26 MB |
| Description | Dual Positive-Edge-Triggered D-Type Flip-Flops |
| Datasheet | SN54AS74A SN54ALS74A Datasheet (PDF) |
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Overview: SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SDAS143C − APRIL 1982 − REVISED AUGUST 1995 • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE ′ALS74A ′AS74A TYPICAL MAXIMUM CLOCK FREQUENCY (CL = 50 pF) (MHz) 50 134 TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 6 26 SN54ALS74A, SN54AS74A . . . J PACKAGE SN74ALS74A, SN74AS74A . . .
This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | SN54AS74A |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 1.26 MB |
| Description | Dual Positive-Edge-Triggered D-Type Flip-Flops |
| Datasheet | SN54AS74A SN54ALS74A Datasheet (PDF) |
|
|
|
These devices contain two independent positive-edge-triggered D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
| Part Number | Description |
|---|---|
| SN54AS756 | Octal Buffers Line Drivers |
| SN54AS760 | Octal Buffers Line Drivers |
| SN54AS00 | Quadruple 2-Input Positive-NAND Gates |
| SN54AS02 | Quadruple 2-Input Positive-NOR Gates |
| SN54AS04 | Hex Inverters |
| SN54AS08 | Quadruple 2-Input Positive-AND Gates |
| SN54AS10 | Triple 3-Input Positive-NAND Gate |
| SN54AS1000A | Quadruple 2-Input Positive-NAND Buffers/Drivers |
| SN54AS1004A | HEX INVERTING Deiver |
| SN54AS1032A | Quadruple 2-Input Positive-OR Buffers/Drivers |