Texas Instruments SN54AS867
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C.| Part No. | SN54AS867 |
|---|---|
| Datasheet | SN54AS867 Download |
| Manufacturer |  Texas Instruments |
| Description | SYNCHRONOUS 8-BIT UP/DOWN COUNTERS |
| Buy | Stock & Price |
SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
● Fully Programmable With Synchronous Counting and Loading
● SN74ALS867A and ′AS867 Have Asynchronous Clear; SN74ALS869 and ′AS869 Have Synchronous Clear
● Fully Independent Clock Circuit Simplifies Use
● Ripple-Carry Output for n-Bit Cascading
● Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs description These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters.
● Fully Programmable With Synchronous Counting and Loading
● SN74ALS867A and ′AS867 Have Asynchronous Clear; SN74ALS869 and ′AS869 Have Synchronous Clear
● Fully Independent Clock Circuit Simplifies Use
● Ripple-Carry Output for n-Bit Cascading
● Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs description These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters.
