SN54CDC586 Datasheet | Texas Instruments

description The SN54CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz, or down to 25 MHz on outputs configured as half-frequency outputs. The SN54CDC586 Woperates at 3.3-V VCC and is designed to drive a properly terminated 50- transmission line. WD PACKAGE (TOP VIEW) NC AVCC AGND FBIN AGND SEL0 SEL1 GND GND 1Y1 VCC GND 1Y2 VCC GND 1Y3 VCC GND GND 2Y1 VCC GND 2Y2 VCC GND 2Y3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 NC 55 CLKIN 54 NC 53 AVCC 52 OE 51 TEST 50 CLR 49 VCC 48 4Y3 47 GND 46 VCC 45 4Y2 44 GND 43 VCC 42 4Y1 41 GND 40 GND 39 VCC 38 3Y3 37 GND 36 VCC 35 3Y2 34 GND 33 VCC 32 3Y1 31 GND 30 GND 29 NC - No internal connection The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input. The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are adjusted to 50%, independent of the duty cycle at CLKIN. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication...