SN54F138 Datasheet | Texas Instruments

description The ′F138 is designed to be used in high-performance memory-decoding or datarouting applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. SDFS051B - MARCH 1987 - REVISED JULY 1996 SN54F138 . . . J PACKAGE SN74F138 . . . D OR N PACKAGE (TOP VIEW) A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 SN54F138 . . . FK PACKAGE (TOP VIEW) Y0 C G2A NC G2B G1 3 2 1 20 19 18 Y1 17 Y2 16 NC 15 Y3 14 Y4 9 10 11 12 13 Y5 Y6 Y7 The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or - No internal connection inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54F138 is characterized for operation over the full military temperature range of - 55°C to 125°C. The SN74F138 is characterized for operation from 0°C to...