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SN54F74J - DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

Download the SN54F74J datasheet PDF. This datasheet also covers the SN54F74 variant, as both devices belong to the same dual positive-edge-triggered d-type flip-flops family and are provided as variant models within a single manufacturer datasheet.

General Description

These devices contain two independent positiveedge-triggered D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.

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Note: The manufacturer provides a single datasheet file (SN54F74-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
SN54F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54F00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SN54F02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SN54F04 HEX INVERTERS
SN54F10 TRIPLE 3-INPUT POSITIVE-NAND GATE

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SDFS046A – MARCH 1987 – REVISED OCTOBER 1993 • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent positiveedge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse.