SN54LV74 Datasheet | Texas Instruments

SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C - FEBRUARY 1993 - REVISED APRIL 1996 D EPIC ™ (Enhanced-Performance Implanted CMOS) 2-µ Process D Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C D Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C D ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 D Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs description These dual positive-edge-t...