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SN65EPT23 - 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator

General Description

The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device.

The device includes circuitry to maintain inputs at Vcc/2 when left open.

The SN65EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option.

Key Features

  • 1.
  • Dual 3.3 V Differential LVPECL/LVDS to LVTTL/LVCMOS Buffer Translator.
  • 24 mA LVTTL Ouputs.
  • Operating Range.
  • VCC = 3.0 V to 3.6 V.
  • GND = 0 V.
  • Support for Clock Frequencies > 300 MHz.
  • 2.0 ns Typical Propagation Delay.
  • Built-in Temperature Compensation.
  • Drop in Compatible to MC100EPT23.

📥 Download Datasheet

Datasheet Details

Part number SN65EPT23
Manufacturer Texas Instruments
File Size 544.36 KB
Description 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator
Datasheet download datasheet SN65EPT23 Datasheet

Full PDF Text Transcription for SN65EPT23 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SN65EPT23. For precise diagrams, and layout, please refer to the original PDF.

SN65EPT23 www.ti.com SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator Check for Samples: SN65EPT23 FEATURES 1 ...

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DS to LVTTL/LVCMOS Translator Check for Samples: SN65EPT23 FEATURES 1 • Dual 3.3 V Differential LVPECL/LVDS to LVTTL/LVCMOS Buffer Translator • 24 mA LVTTL Ouputs • Operating Range – VCC = 3.0 V to 3.6 V – GND = 0 V • Support for Clock Frequencies > 300 MHz • 2.0 ns Typical Propagation Delay • Built-in Temperature Compensation • Drop in Compatible to MC100EPT23 APPLICATIONS • Data and Clock Transmission Over Backplane • Signaling Level Conversion for Clock or Data DESCRIPTION The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device. The device includes circuitry to maintain inputs at Vcc/2 when left

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