SN65LV1212 Overview
The SN65LV1021 serializer and SN65LV1212 deserializer prise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 40 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 480-Mbps payload-encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode...
SN65LV1212 Key Features
- 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock
- Pin-patible Superset of NSM DS92LV1021/DS92LV1212
- Chipset (Serializer/Deserializer) Power Consumption <350 mW (Typ) at 40 MHz
- Synchronization Mode for Faster Lock
- Lock Indicator
- No External ponents Required for PLL
- Low-Cost 28-Pin SSOP Package
- Industrial Temperature Qualified
- Programmable Edge Trigger on Clock
- Flow-Through Pinout for Easy PCB Layout