SN65LVDM31 Datasheet | Texas Instruments

FEATURES - Designed for Signaling Rates NOTE: The signaling rate is the number of voltage transitions that can be made per second. Up to 150 Mbps - Low-Voltage Differential Signaling With Typical Output Voltage of 700 m V and a 100-Ω Load - Propagation Delay Time of 2.3 ns, Typical - Single 3.3-V Supply Operation - One Driver's Power Dissipation at 75 MHz, 50 m W, Typical - High-Impedance Outputs When Disabled or With VCC < 1.5 V - Bus-Pin ESD Protection Exceeds 12 k V - Low-Voltage CMOS (LVCMOS) Logic Input Levels Are 5-V Tolerant DESCRIPTION The SN65LVDM31 incorporates four differential line drivers that implement the electrical characteristics of low-voltage differential signaling. This product offers a low-power alternative to 5-V PECL drivers with similar signal levels. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 540 m V into a 100-Ω load when enabled by either an active-low or active-high enable input. The intended application of this device and signaling technique is for both point-to-point and multiplexed baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDM31 is characterized for operation from - 40°C to 85°C. SN65LVDM31D (Marked as LVDM31) (TOP VIEW) 1A 1 1Y 2 1Z 3 G4 2Z 5 2Y 6 2A 7 GND 8 16 VCC 15 4A 14 4Y 13 4Z 12 G 11 3Z 10 3Y 9 3A FUNCTIONAL BLOCK DIAGRAM 4 G G 12 1 1A 7 2A 2 1Y 3 1Z 6 2Y 5 2Z 9 3A 10 3Y 11 3Z 15 4A 14 4Y 13 4Z INPUT A H L H L X Open Open FUNCTION...