SN65LVDS109 Overview
The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four ('109) or eight ('117) differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.
SN65LVDS109 Key Features
- Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 S
- Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
- Outputs Arranged in Pairs From Each Bank
- Enabling Logic Allows Individual Control of Each Driver Output Pair, Plus All Outputs
- Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load
- Electrically patible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Terminat
- Propagation Delay Times < 4.5 ns
- Output Skew Less Than 550 ps Bank Skew Less Than150 ps Part-to-Part Skew Less Than 1.5 ns
- Total Power Dissipation Typically <500 mW With All Ports Enabled and at 200 MHz
- Driver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC < 1.5 V