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SN65LVDS310 - PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

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General Description

The SN65LVDS310 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs.

Overview

www.ti.com SN65LVDS310 SLLS836 – MAY 2007 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL.

Key Features

  • Serial Interface Technology.
  • Compatible With FlatLink™ 3G Transmitters (E. g. , SN65LVDS305 or SN65LVDS307).
  • Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over One SubLVDS Differential Data Line.
  • SubLVDS Differential Voltage Levels.
  • Up to 405-Mbps Data Throughput.
  • Three Operating Modes to Conserve Power.
  • Active mode QVGA: 17 mW.
  • Typical Shutdown: 0.7 µW.
  • Typical Standby Mode: 67 µW Typic.

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