SN65LVDS4 Datasheet | Texas Instruments

Features - 1 Designed for Signaling Rates up to: - 500-Mbps Receiver (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second) - Operates From a 1.8-V or 2.5-V Core Supply - Available in 1.5-mm × 2-mm UQFN Package - Bus-Terminal ESD Exceeds 2 k V (HBM) - Low-Voltage Differential Signaling With Typical Output Voltages of 350 m V Into a 100-Ω Load - Propagation Delay Times - 2.1 ns Typical Receiver - Power Dissipation at 250 MHz - 40 m W Typical - Requires External Failsafe - Differential Input Voltage Threshold Less Than 50 m V - Can Provide Output Voltage Logic Level (3.3-V LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based on External VDD Pin, Thus Eliminating External Level Translation 2 Applications - Clock Distribution - Wireless Base Stations - Network Routers 3 Description The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) UQFN (10) 1.50 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Circuits An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SLLSE15A - JULY 2011 - REVISED NOVEMBER 2015 .ti. Table of Contents 1 Features 1 2 Applications 1 3...