SN65LVDT3486B Overview
Description
This family of differential line receivers offers improved performance and features that implement the D PACKAGE (TOP VIEW) SN65LVDS32B SN65LVDT32B Logic Diagram (positive logic) 1B 1 1A 2 16 VCC 15 4B G G SN65LVDT32B 1Y 3 14 4A ONLY (4 Places) 1A G 4 13 4Y 1Y 2Y 5 12 G 1B 2A 6 11 3Y 2A 2B 7 10 3A 2Y GND 8 9 3B 2B 3A 3Y 3B 4A 4Y 4B SN65LVDS3486B SN65LVDT3486B D PACKAGE Logic Diagram (TOP VIEW) (positive logic) SN65LVDT3486B 1B 1 16 VCC ONLY (4 Places) 1A 2 15 4B 1A 1Y 1Y 3 14 4A 1B 1,2EN 4 13 4Y 1,2EN 2Y 5 12 3,4EN 2A 2Y 2A 6 11 3Y 2B 2B 7 10 3A GND 8 9 3B 3A 3Y.
Key Features
- Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates (1) up to 400 Mbps
- Operates With a Single 3.3-V Supply
- 2-V to 4.4-V Common-Mode Input Voltage Range
- Differential Input Thresholds <50 mV With 50 mV of Hysteresis Over Entire CommonMode Input Voltage Range
- Integrated 110-Ω Line Termination Resistors Offered With the LVDT Series
- Propagation Delay Times 4 ns (typ)
- Active Fail Safe Assures a High-Level Output With No Input
- Bus-Pin ESD Protection Exceeds 15 kV HBM
- Inputs Remain High-Impedance on Power Down
- Recommended Maximum Parallel Rate of 200 M-Transfer/s
