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SN65LVP20 - LVPECL AND LVDS REPEATER/TRANSLATOR

Download the SN65LVP20 datasheet PDF. This datasheet also covers the SN65LVDS20 variant, as both devices belong to the same lvpecl and lvds repeater/translator family and are provided as variant models within a single manufacturer datasheet.

General Description

The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater.

The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal.

Key Features

  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs.
  • Signaling Rates to 4 Gbps or Clock Rates to 2 GHz.
  • 120-ps Output Transition Times.
  • Less than 45 ps Total Jitter.
  • Less than 630 ps Propagation Delay Times.
  • 2.5-V or 3.3-V Supply Operation.
  • 2-mm x 2-mm Small-Outline No-Lead Package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN65LVDS20-etcTI.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com SN65LVDS20 SN65LVP20 SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 LVPECL AND LVDS REPEATER/TRANSLATOR WITH ENABLE FEATURES • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs • Signaling Rates to 4 Gbps or Clock Rates to 2 GHz – 120-ps Output Transition Times – Less than 45 ps Total Jitter – Less than 630 ps Propagation Delay Times • 2.5-V or 3.3-V Supply Operation • 2-mm x 2-mm Small-Outline No-Lead Package APPLICATIONS • PECL-to-LVDS Translation • Data or Clock Signal Amplification DESCRIPTION The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal.