SN65MLVD128 Datasheet | Texas Instruments

FEATURES - LVTTL Receiver and Eight Line Drivers Configured as an 8-Port M-LVDS Repeater - SN65MLVD128 - 2 LVTTL Receivers and Eight Line Drivers Configured as Dual 4-Port M-LVDS Repeaters - SN65MLVD129 - Drivers Meet or Exceed the M-LVDS Standard (TIA/EIA-899) - Low-Voltage Differential 30-Ω to 55-Ω Line Drivers for Data Rates (1) Up to 250 Mbps or Clock Frequencies Up to 125 MHz - Power Up/Down Glitch Free - Controlled Driver Output Voltage Transition Times for Improved Signal Quality (1) The data rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second). - Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V - Independent Enables for each Driver - Output-to-Ouput Skew tsk(o) ≤ 160 ps Part-to-Part Skew tsk(pp) ≤ 800 ps - Single 3.3-V Voltage Supply - Bus Pin ESD Protection Exceeds 9 k V - Packaged in 48-Pin TSSOP (DGG) APPLICATIONS - Advanced TCA™ (ATCA™) Clock Bus Driver - Clock Distribution - Data and Clock Repeating Over Backplanes and Cables - Cellular Base Stations - Central Office Switches - Network Switches and Routers LOGIC DIAGRAM EN1 EN2 EN3 EN4 1D EN5 EN6 EN7 EN8 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B SN65MLVD128 EN1 EN2 1D EN3 EN4 EN5 EN6 2D EN7 EN8 1A 1B 2A...