SN74125 Overview
Key Specifications
Package: PDIP
Description
These bus buffers feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL output with additional drive capability at high logic levels to permit driving heavily loaded bus lines without external pullup resistors. When disabled, both output transistors are turned off, presenting a high-impedance state to the bus so the output will act neither as a significant load nor as a driver.
Key Features
- The ’125 and ’LS125A devices’ outputs are disabled when G is high
- The ’126 and ’LS126A devices’ outputs are disabled when G is low
- SN54125, SN54126, SN54LS125A, SN54LS126A
- J OR W PACKAGE SN74125, SN74126
- N PACKAGE SN74LS125A, SN74LS126A
