SN74ABT125
description
/ordering information
- No internal connection
The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
PACKAGE†
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PDIP
- N
Tube
SN74ABT125N
SN74ABT125N
- 40°C to 85°C
- RGY
SOIC
- D SOP
- NS SSOP
- DB
Tape and...
