SN74ABT162500 Datasheet | Texas Instruments

description These 18-bit universal bus transceivers bine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. SN54ABT162500 . . . WD PACKAGE SN74ABT162500 . . . DL PACKAGE (TOP VIEW) OEAB 1 LEAB 2 A1 3 GND 4 A2 5 A3 6 VCC 7 A4 8 A5 9 A6 10 GND 11 A7 12 A8 13 A9 14 A10 15 A11 16 A12 17 GND 18 A13 19 A14 20 A15 21 VCC 22 A16 23 A17 24 GND 25 A18 26 OEBA 27 LEBA 28 56 GND 55 CLKAB 54 B1 53 GND 52 B2 51 B3 50 VCC 49 B4 48 B5 47 B6 46 GND 45 B7 44 B8 43 B9 42 B10 41 B11 40 B12 39 GND 38 B13 37 B14 36 B15 35 VCC 34 B16 33 B17 32 GND 31 B18 30 CLKBA 29 GND For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are plementary (OEAB is active high and OEBA is active low). The B-port outputs, which are designed to source or sink up to 12 m A, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does...