Description
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
Features
- Controlled Baseline.
- One Assembly/Test Site, One Fabrication Site.
- Extended Temperature Performance of.
- 55°C to 125°C.
- Enhanced Diminishing Manufacturing Sources (DMS) Support.
- Enhanced Product-Change Notification.
- Qualification Pedigree (1).
- State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Reduces Power Dissipation.
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17.
- ESD Protection Exceed.