SN74AC563 Datasheet PDF

D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 9 ns at 5 V D 3-State Inverting Outputs Drive Bus Lines Directly D Full Parallel Access for Loading D Flow-Through Architecture to Optimize PCB Layout description/ordering information When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 8D GND CLK 8Q SN54AC563, SN74AC563 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003 SN54AC563 . . .