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D Dual Independent FIFOs Organized as:
64 Words by 1 Bit Each – SN74ACT2226
256 Words by 1 Bit Each – SN74ACT2228
D Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident on Each
FIFO
D Input-Ready Flags Synchronized to Write
Clocks
D Output-Ready Flags Synchronized to Read
Clocks
D Half-Full and Almost-Full/Almost-Empty
Flags
D Support Clock Frequencies up to 22 MHz D Access Times of 20 ns D Low-Power Advanced CMOS Technology D Packaged in 24-Pin Small-Outline
Integrated-Circuit Package
SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219C – JUNE 1992 – REVISED OCTOBER 1997
DW PACKAGE (TOP VIEW)
1HF 1 1AF/AE 2 1WRTCLK 3 1WRTEN 4
1IR 5 1D 6 GND 7 1RESET 8 2Q 9 2OR 10 2RDEN 11 2RDCLK 12
24 1RDCLK 23 1RDEN 22 1OR 21 1Q 20 2RESET 19
SN74ACT2226 Datasheet
