SN74ACT563 Datasheet PDF

SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 8.5 ns at 5 V D Inputs Are TTL-Voltage Compatible D 3-State Inverted Outputs Drive Bus Lines Directly D Flow-Through Architecture to Optimize PCB Layout description/ordering information When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs. SN54ACT563 . . . J OR W PACKAGE SN74ACT563 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE SN54ACT563 . . . FK PACKAGE (TOP VIEW) 1Q VCC OE 1D 2D A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components.