SN74ACT8990 Datasheet | Texas Instruments

description The ’ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPE™ testability integrated-circuit family. This family of ponents supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of plex circuit-board assemblies. The ’ACT8990 differ from other SCOPE™ integrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary -scannable devices. The required signals of the JTAG serial-test bus - test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable ponents that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5 - 0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing mon TCK, TDI, and TDO signals). While most operations of the TBC are synchronous to TCKI, a test-off (TOFF) input is provided for output control of the target interface, and a test-reset (TRST) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3 - 0)] I/Os are provided for asynchronous munication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters. The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4 - 0)] and the 16-bit read/write data bus [DATA (15 - 0)]. Read (RD) and write (WR) strobes are implemented such that the...