SN74AHC02-EP Datasheet | Texas Instruments

SN74AHC02-EP QUADRUPLE 2-INPUT POSITIVE-NOR GATES D Controlled Baseline - One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of - 55°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Operating Range 2-V to 5.5-V VCC D Latch-Up Performance Exceeds 250 m A Per JESD 17 † ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. SCLS480 - MAY 2003 D ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) PW PACKAGE (TOP VIEW) 1Y 1 1A 2 1B 3 2Y 4 2A 5 2B 6 GND 7 14 VCC 13 4Y 12 4B 11 4A 10 3Y 9 3B 8 3A description/ordering information The ’AHC02 device contains four independent 2-input NOR gates that perform the Boolean function Y = A S B or Y = A + B in positive logic. ORDERING INFORMATION PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING - 55°C to 125°C TSSOP - PW Tape and reel SN74AHC02MPWREP AHC02EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at .ti./sc/package. FUNCTION TABLE (each...