SN74ALS169B Datasheet | Texas Instruments

description SDAS125B - MARCH 1984 - REVISED DECEMBER 1994 SN54ALS169B, SN54AS169A . . . J PACKAGE SN74ALS169B, SN74AS169A . . . D OR N PACKAGE (TOP VIEW) U/D 1 CLK 2 A3 B4 C5 D6 ENP 7 GND 8 16 VCC 15 RCO 14 QA 13 QB 12 QC 11 QD 10 ENT 9 LOAD These synchronous 4-bit up/down binary presettable counters feature an internal carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. SN54ALS169B, SN54AS169A . . . FK PACKAGE (TOP VIEW) CLK U/D NC VCC RCO 3 2 1 20 19 A4 18 QA B5 17 QB NC 6 16 NC C7 15 QC 9 10 11 12 13 ENP GND NC LOAD These counters are fully programmable; that is, they may be preset to either level. The load-input circuitry allows loading with the carry-enable output of cascaded counters. Because loading is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. - No internal connection The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in acplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting down or maximum (15)...