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SN74ALS74A - Dual Positive-Edge-Triggered D-Type Flip-Flops

Description

These devices contain two independent positive-edge-triggered D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.

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Full PDF Text Transcription

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SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SDAS143C − APRIL 1982 − REVISED AUGUST 1995 • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE ′ALS74A ′AS74A TYPICAL MAXIMUM CLOCK FREQUENCY (CL = 50 pF) (MHz) 50 134 TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 6 26 SN54ALS74A, SN54AS74A . . . J PACKAGE SN74ALS74A, SN74AS74A . . . D OR N PACKAGE (TOP VIEW) 1CLR 1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6 GND 7 14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q description These devices contain two independent positive-edge-triggered D-type flip-flops.
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