SN74ALVC162836 Datasheet | Texas Instruments

.ti. Features - Member of the Texas Instruments Widebus™ Family - Operates From 1.65 V to 3.6 V - Max tpd of 4 ns at 3.3 V - ±12-m A Output Drive at 3.3 V - Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required - Designed to ply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification - Latch-Up Performance Exceeds 250 m A Per JESD 17 - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129E - MARCH 1998 - REVISED OCTOBER 2004 DGG, DGV, OR DL PACKAGE (TOP VIEW) OE 1 Y1 2 Y2 3 GND 4 Y3 5 Y4 6 VCC 7 Y5 8 Y6 9 Y7 10 GND 11 Y8 12 Y9 13 Y10 14 Y11 15 Y12 16 Y13 17 GND 18 Y14 19 Y15 20 Y16 21 VCC 22 Y17 23 Y18 24 GND 25 Y19 26 Y20 27 NC 28 56 CLK 55 A1 54 A2 53 GND 52 A3 51 A4 50 VCC 49 A5 48 A6 47 A7 46 GND 45 A8 44 A9 43 A10 42 A11 41 A12 40 A13 39 GND 38 A14 37 A15 36 A16 35 VCC 34 A17 33 A18 32 GND 31 A19 30 A20 29 LE - No internal connection TA -40°C to 85°C ORDERING...