SN74ALVCH16270 Datasheet | Texas Instruments

FEATURES - Member of the Texas Instruments Widebus™ Family DGG OR DL PACKAGE (TOP VIEW) - EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process - Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) - Latch-Up Performance Exceeds 250 m A Per JESD 17 - Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DESCRIPTION This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus-direction changes with CLK. OEA 1 CLKEN1B 2 2B3 3 GND 4 2B2 5 2B1 6 VCC 7 A1 8 A2 9 A3 10 GND 11 A4 12 A5 13 A6 14 A7 15 A8 16 A9 17 GND 18 A10 19 A11 20 A12 21 VCC 22 1B1 23 1B2 24 GND 25 1B3 26 CLKEN2B 27 SEL 28 56 OEB 55 CLKENA2 54 2B4 53 GND 52 2B5 51 2B6 50 VCC 49 2B7 48 2B8 47 2B9 46 GND 45 2B10 44 2B11 43 2B12 42 1B12 41 1B11 40 1B10 39 GND 38 1B9 37 1B8 36 1B7 35 VCC 34 1B6 33 1B5 32 GND 31 1B4 30 CLKENA1 29 CLK line space To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and...