SN74ALVCH16601 Datasheet | Texas Instruments

FEATURES - Member of the Texas Instruments Widebus™ Family DGG OR DL PACKAGE (TOP VIEW) - UBT™ (Universal Bus Transceiver) bines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes - EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) - Latch-Up Performance Exceeds 250 m A Per JESD 17 - Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors - Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DESCRIPTION This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16601 bines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. OEAB 1 LEAB 2 A1 3 GND 4 A2 5 A3 6 VCC 7 A4 8 A5 9 A6 10 GND 11 A7 12 A8 13 A9 14 A10 15 A11 16 A12 17 GND 18 A13 19 A14 20 A15 21 VCC 22 A16 23 A17 24 GND 25 A18 26 OEBA 27 LEBA 28 56 CLKENAB 55 CLKAB 54 B1 53 GND 52 B2 51 B3 50 VCC 49 B4 48 B5 47 B6 46 GND 45 B7 44 B8 43 B9 42 B10 41 B11 40 B12 39 GND 38 B13 37 B14 36 B15 35 VCC 34 B16 33 B17 32 GND 31 B18 30 CLKBA 29 CLKENBA <br/> Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and...