SN74ALVCH16835 Datasheet | Texas Instruments

FEATURES - Member of the Texas Instruments Widebus™ Family - Operates From 1.65 V to 3.6 V - Max tpd of 3.6 ns at 3.3 V - ±24-m A Output Drive at 3.3 V - Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors - Latch-Up Performance Exceeds 250 m A Per JESD 17 - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) DESCRIPTION /ORDERING INFORMATION This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not xxxx remended. xxxx SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053J - SEPTEMBER 1995 - REVISED OCTOBER 2004 DGG, DGV, OR DL PACKAGE (TOP VIEW) NC 1 NC 2 Y1 3 GND 4 Y2 5 Y3 6 VCC 7 Y4 8 Y5 9 Y6 10 GND 11 Y7 12 Y8 13 Y9 14 Y10 15 Y11 16 Y12 17 GND 18 Y13 19 Y14 20 Y15 21 VCC 22 Y16 23 Y17 24 GND 25 Y18 26 OE 27 LE 28 56 GND 55 NC 54 A1 53 GND 52 A2 51 A3 50 VCC 49 A4 48 A5 47 A6 46 GND 45 A7 44 A8 43 A9 42 A10 41 A11 40 A12 39 GND 38 A13 37 A14 36 A15 35 VCC 34 A16 33 A17 32 GND 31 A18 30 CLK 29 GND - No internal connection TA -40°C to 85°C ORDERING INFORMATION PACKAGE (1) ORDERABLE PART NUMBER SSOP - DL Tube Tape and reel SN74ALVCH16835DL SN74ALVCH16835DLR TSSOP - DGG Tape and...