Texas Instruments SN74AS137
The SN74ALS137A and SN74AS137 are characterized for operation from 0°C to 70°C. SN54ALS137A, SN74ALS137A, SN74AS137 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES SDAS203C − APRIL 1982 − REVISED JANUARY 1995 • Combines Decoder and 3-Bit Address Latch • Incorporates Two Output Enables to Simplify Cascading • Package Options Include Plastic Small- Outline (D)...| Part No. | SN74AS137 |
|---|---|
| Datasheet | SN74AS137 Download |
| Manufacturer |  Texas Instruments |
| Description | 3-Line To 8-Line Decoders/Demultiplexers |
| Buy | Stock & Price |
SN54ALS137A, SN74ALS137A, SN74AS137 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES SDAS203C − APRIL 1982 − REVISED JANUARY 1995
● Combines Decoder and 3-Bit Address Latch
● Incorporates Two Output Enables to Simplify Cascading
● Package Options Include Plastic Small- Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/ demultiplexers with latches on the three address inputs. When the latch-enable (LE) input is low, the devices act as decoders/demultiplexers. When LE goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as LE remains high. The output-enable controls (G1 and G2) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2 is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.
● Combines Decoder and 3-Bit Address Latch
● Incorporates Two Output Enables to Simplify Cascading
● Package Options Include Plastic Small- Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs description The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/ demultiplexers with latches on the three address inputs. When the latch-enable (LE) input is low, the devices act as decoders/demultiplexers. When LE goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as LE remains high. The output-enable controls (G1 and G2) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2 is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.
