SN74AS825A Datasheet | Texas Instruments

description SN54AS825A, SN74AS825A 8ĆBIT BUSĆINTERFACE FLIPĆFLOPS WITH 3ĆSTATE OUTPUTS SDAS020B - JUNE 1984 - REVISED AUGUST 1995 SN54AS825A . . . JT PACKAGE SN74AS825A . . . DW OR NT PACKAGE (TOP VIEW) OE1 1 OE2 2 1D 3 2D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D 10 CLR 11 GND 12 24 VCC 23 OE3 22 1Q 21 2Q 20 3Q 19 4Q 18 5Q 17 6Q 16 7Q 15 8Q 14 CLKEN 13 CLK These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing multiuser registers, I/O ports, bidirectional bus drivers, and working registers. With the clock-enable (CLKEN) input low, the eight D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking CLKEN high disables the clock buffer, latching the outputs. These devices have noninverting data (D) inputs. Taking the clear (CLR) input low causes the eight Q outputs to go low independently of the clock. SN54AS825A . . . FK PACKAGE (TOP VIEW) 1D OE2 OE1 NC VCC OE3 1Q 4 3 2 1 28 27 26 2D 5 25 2Q 3D 6 24 3Q 4D 7 23 4Q NC 8 22 NC 5D 9 21 5Q 6D 10 20 6Q 7D 11 19 7Q 12 13 14 15 16 17 18 8D CLR GND NC CLK CLKEN 8Q Multiuser buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without interface or pullup ponents. - No internal connection The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS825A is characterized for operation over the full military temperature range...