SN74AS867 Datasheet | Texas Instruments

description These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positivegoing) edge of the clock waveform. These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. SN54AS867, SN54AS869 . . . JT PACKAGE SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 . . . DW OR NT PACKAGE (TOP VIEW) S0 1 S1 2 A3 B4 C5 D6 E7 F8 G9 H 10 ENT 11 GND 12 24 VCC 23 ENP 22 QA 21 QB 20 QC 19 QD 18 QE 17 QF 16 QG 15 QH 14 CLK 13 RCO SN54AS867, SN54AS869 . . . FK PACKAGE (TOP VIEW) A S1 S0 NC VCC ENP QA 4 3 2 1 28 27 26 B5 25 QB C6 24 QC D7 23 QD NC 8 22 NC E9 21 QE F 10 20 QF G 1112 13 14 15 16 17 1819 QG H ENT GND NC RCO CLK - No internal connection The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output are instrumental in acplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined by the levels of the select (S0, S1) inputs as shown in the function table. ENT is fed forward to enable RCO. RCO thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all...