SN74AUC126 Description
/ORDERING INFORMATION This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCC operation, but is designed specifically for 1.6-V to 1.95-V VCC operation. The SN74AUC126 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
SN74AUC126 Key Features
- Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub 1-V Operable
- Max tpd of 2.1 ns at 1.8 V
- Low Power Consumption, 10-µA Max ICC
- ±8-mA Output Drive at 1.8 V
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)