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SN74AUC1G04 - Single Inverter Gate

General Description

This single inverter gate is operational at 0.8-V to 2.7V VCC, but is designed specifically for 1.65-V to 1.95V VCC operation.

The SN74AUC1G04 performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Key Features

  • 1 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD Protection Exceeds JESD 22.
  • 2000-V Human-Body Model (A114-A).
  • 200-V Machine Model (A115-A).
  • 1000-V Charged-Device Model (C101).
  • Available in the Texas Instruments NanoFree™ Package.
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation.
  • Ioff Supports Partial Power Down Mode and Back Drive Protection.
  • Sub-1-V Ope.

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Other Datasheets by Texas Instruments

Part Number Description
SN74AUC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE
SN74AUC1G02 SINGLE 2-INPUT POSITIVE-NOR GATE
SN74AUC1G06 SINGLE INVERTER BUFFER/DRIVER
SN74AUC1G07 Single Buffer/Driver
SN74AUC1G08 Single 2-Input Positive-AND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Order Now Technical Documents Tools & Software Support & Community SN74AUC1G04 SCES370R – SEPTEMBER 2001 – REVISED JUNE 2017 SN74AUC1G04 Single Inverter Gate 1 Features •1 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • Available in the Texas Instruments NanoFree™ Package • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial Power Down Mode and Back Drive Protection • Sub-1-V Operable • Max tpd of 2.2 ns at 1.8 V • Low Power Consumption, 10-µA Maximum ICC • ±8-mA Output Drive at 1.