SN74AUC1G240 Datasheet | Texas Instruments

FEATURES - Available in the Texas Instruments Nano Free™ Package - Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation - Ioff Supports Partial-Power-Down Mode Operation - Sub-1-V Operable - Max tpd of 2.5 ns at 1.8 V DBV PACKAGE (TOP VIEW) - Low Power Consumption, 10-µA Max ICC - ±8-m A Output Drive at 1.8 V - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) GND 3 4 Y A2 OE 1 5 VCC 4Y See mechanical drawings for dimensions. DESCRIPTION /ORDERING INFORMATION This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G240 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Nano Free™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION - 40°C to 85°C PACKAGE (1) Nano Free™ - WCSP (DSBGA) 0.23-mm Large...