SN74AUC1G86 Datasheet | Texas Instruments

FEATURES - 2 Available in the Texas Instruments Nano Free™ Package - Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation - Ioff Supports Partial Power-Down-Mode Operation - Sub-1-V Operable - Max tpd of 2.5 ns at 1.8 V - Low Power Consumption, 10-µA Max ICC - ±8-m A Output Drive at 1.8 V - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) DBV PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) GND 3 4 Y B2 A 15 4Y See mechanical drawings for dimensions. DESCRIPTION /ORDERING INFORMATION This single 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic. A mon application is as a true/plement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. Nano Free™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. - 40°C to 85°C ORDERING INFORMATION PACKAGE (1) (2) ORDERABLE PART...