SN74AUP2G07 Description
The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V. 1A 1Y 2A 2Y Simplified Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. SN74AUP2G07 SCES748E SEPTEMBER 2009 REVISED OCTOBER 2021 .ti.
SN74AUP2G07 Key Features
- Low static-power consumption (ICC = 0.9 µA maximum)
- Low dynamic-power consumption (Cpd = 1 pF typical at 3.3 V)
- Low input capacitance (Ci = 1.5 pF typical)
- Low noise
- overshoot and undershoot
- Ioff supports live insertion, partial-power-down
- Input hysteresis allows slow input transition and
- Wide operating VCC range of 0.8 V to 3.6 V
- Optimized for 3.3 V operation
- 3.6-V I/O tolerant to support mixed-mode signal operation
SN74AUP2G07 Applications
- Latch-up performance exceeds 100 mA per JESD 78, Class II
- ESD performance tested per JESD 22