SN74BCT29854 Datasheet | Texas Instruments

description The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous munication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic. The SN74BCT29854 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS Ai ∑ of H’s Bi† ∑ of L’s OUTPUT AND I/O B PARITY ERR‡ Odd Even Odd Even N- 1 X L Odd H Even Odd Even NA = not applicable, NC = no change, X = don’t care † Summation of low-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume the ERR output was previously high. - In this mode, the ERR output, when enabled, shows noninverted parity of the A bus. FUNCTION A data to B bus and generate parity B data to A bus and check parity Store error flag Clear error-flag register Isolation- A data to B bus and generate inverted parity PRODUCTION DATA information is current as of publication date. Products...